// ******************************************************************************
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_sdma_ns_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2
// History       :  xxx 2021/10/23 09:25:46 Create file
// ******************************************************************************

#ifndef __STARS_SDMA_NS_REG_REG_OFFSET_H__
#define __STARS_SDMA_NS_REG_REG_OFFSET_H__

/* STARS_SDMA_NS_REG Base address of Module's Register */
#define SOC_STARS_SDMA_NS_REG_BASE                       (0x2c10000)

/******************************************************************************/
/*                      SOC STARS_SDMA_NS_REG Registers' Definitions                            */
/******************************************************************************/

#define SOC_STARS_SDMA_NS_REG_STARS_PRIORITY_CTRL0_REG            (SOC_STARS_SDMA_NS_REG_BASE + 0x0)
#define SOC_STARS_SDMA_NS_REG_STARS_PRIORITY_CTRL1_REG            (SOC_STARS_SDMA_NS_REG_BASE + 0x4)
#define SOC_STARS_SDMA_NS_REG_STARS_PRIORITY_CTRL2_REG            (SOC_STARS_SDMA_NS_REG_BASE + 0x8)
#define SOC_STARS_SDMA_NS_REG_STARS_PRIORITY_CTRL3_REG            (SOC_STARS_SDMA_NS_REG_BASE + 0xC)
#define SOC_STARS_SDMA_NS_REG_STARS_FRIENDLY_CTRL_REG             (SOC_STARS_SDMA_NS_REG_BASE + 0x20)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_BLK_FSM_SEL_REG          (SOC_STARS_SDMA_NS_REG_BASE + 0x810)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_BLK_FSM_STATE_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x814)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_REDUNDANT_RSP_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x820)
#define SOC_STARS_SDMA_NS_REG_STARS_FREE_SDMA_SQ_BITMAP_REG       (SOC_STARS_SDMA_NS_REG_BASE + 0x824)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_DFX_CNT_ENABLE_REG       (SOC_STARS_SDMA_NS_REG_BASE + 0x830) /* SDMA调度器任务总数统计使能寄存器 */
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_DFX_TASK_VLD_CNT_REG     (SOC_STARS_SDMA_NS_REG_BASE + 0x834) /* SDMA调度器下发任务总数 */
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_DFX_TASK_RSP_CNT_REG     (SOC_STARS_SDMA_NS_REG_BASE + 0x838) /* SDMA调度器收到加速器完成响应总数 */
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_POOL_ENABLE_CTRL_NS_REG  (SOC_STARS_SDMA_NS_REG_BASE + 0x840)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_POOL_DISABLE_CTRL_NS_REG (SOC_STARS_SDMA_NS_REG_BASE + 0x880)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_POOL_STATUS0_NS_REG      (SOC_STARS_SDMA_NS_REG_BASE + 0x8C0)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS0_0_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x940)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS0_1_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x980)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS0_2_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x9C0)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS0_3_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA00)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS0_4_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA40)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS0_5_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA80)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS1_0_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x944)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS1_1_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x984)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS1_2_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x9C4)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS1_3_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA04)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS1_4_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA44)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS1_5_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA84)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS2_0_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x948)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS2_1_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x988)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS2_2_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x9C8)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS2_3_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA08)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS2_4_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA48)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS2_5_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA88)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS3_0_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x94C)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS3_1_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x98C)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS3_2_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0x9CC)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS3_3_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA0C)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS3_4_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA4C)
#define SOC_STARS_SDMA_NS_REG_STARS_SDMA_CQE_STATUS3_5_REG        (SOC_STARS_SDMA_NS_REG_BASE + 0xA8C)

#endif // __STARS_SDMA_NS_REG_REG_OFFSET_H__
